detailed results (1648 total)

prover file res expected time
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_8clocks.worst_case_skew.base.smt2 (content) unsat unsat 0.007s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_8clocks.main_invar.induct.smt2 (content) timeout unsat 10s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_8clocks.main_invar.base.smt2 (content) unsat unsat 0.804s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_7clocks.worst_case_skew.induct.smt2 (content) timeout unsat 10s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_7clocks.worst_case_skew.base.smt2 (content) unsat unsat 0.020s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_7clocks.main_invar.induct.smt2 (content) timeout unsat 10s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_7clocks.main_invar.base.smt2 (content) unsat unsat 0.457s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_6clocks.worst_case_skew.induct.smt2 (content) timeout unsat 10s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_6clocks.worst_case_skew.base.smt2 (content) unsat unsat 0.008s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_6clocks.main_invar.induct.smt2 (content) timeout unsat 10s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_6clocks.main_invar.base.smt2 (content) unsat unsat 0.284s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_5clocks.worst_case_skew.induct.smt2 (content) timeout unsat 10s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_5clocks.worst_case_skew.base.smt2 (content) unsat unsat 0.009s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_5clocks.main_invar.induct.smt2 (content) timeout unsat 10s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_5clocks.main_invar.base.smt2 (content) unsat unsat 0.211s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_4clocks.worst_case_skew.induct.smt2 (content) timeout unsat 10s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_4clocks.worst_case_skew.base.smt2 (content) unsat unsat 0.017s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_4clocks.main_invar.induct.smt2 (content) timeout unsat 10s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_4clocks.main_invar.base.smt2 (content) unsat unsat 0.115s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_3clocks.worst_case_skew.induct.smt2 (content) timeout unsat 10s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_3clocks.worst_case_skew.base.smt2 (content) unsat unsat 0.007s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_3clocks.main_invar.induct.smt2 (content) timeout unsat 10s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_3clocks.main_invar.base.smt2 (content) unsat unsat 0.084s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_2clocks.worst_case_skew.induct.smt2 (content) timeout unsat 10s
mc2 /home/simon/w/mc2/tests/QF_LRA/clock_synchro/clocksynchro_2clocks.worst_case_skew.base.smt2 (content) unsat unsat 0.008s