show full table

problem	z3	sidekick	mc2	z3.time	sidekick.time	mc2.time
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_at.4.prop1_ab_reg_max.smt2	sat	sat	sat	0.01	0.03	0.02
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_at.5.prop1_ab_cti_max.smt2	sat	sat	sat	0.05	0.19	0.09
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_at.5.prop1_ab_reg_max.smt2	sat	sat	sat	0.01	0.01	0.01
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_at.6.prop1_ab_cti_max.smt2	sat	sat	sat	0.07	0.18	0.10
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_at.6.prop1_ab_reg_max.smt2	sat	sat	sat	0.01	0.01	0.01
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_at.7.prop1_ab_cti_max.smt2	sat	sat	sat	0.06	0.28	0.13
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_at.7.prop1_ab_reg_max.smt2	sat	sat	sat	0.01	0.01	0.01
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bakery.1.prop1_ab_reg_max.smt2	sat	sat	sat	0.02	0.01	0.01
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bakery.2.prop1_ab_reg_max.smt2	sat	sat	sat	0.02	0.01	0.02
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bakery.3.prop1_ab_reg_max.smt2	sat	sat	sat	0.02	0.03	0.02
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bakery.4.prop1_ab_cti_max.smt2	sat	sat	sat	0.02	0.04	0.02
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bakery.4.prop1_ab_reg_max.smt2	sat	sat	sat	0.03	0.01	0.01
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bakery.5.prop1_ab_cti_max.smt2	sat	sat	sat	0.02	0.05	0.04
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bakery.5.prop1_ab_reg_max.smt2	sat	sat	sat	0.01	0.01	0.01
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bakery.6.prop1_ab_cti_max.smt2	sat	sat	sat	0.02	0.07	0.07
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bakery.6.prop1_ab_reg_max.smt2	sat	sat	sat	0.01	0.01	0.01
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bakery.7.prop1_ab_cti_max.smt2	sat	sat	sat	0.02	0.05	0.03
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bakery.7.prop1_ab_reg_max.smt2	sat	sat	sat	0.01	0.01	0.01
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bakery.8.prop1_ab_cti_max.smt2	sat	sat	sat	0.03	0.07	0.05
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bakery.8.prop1_ab_reg_max.smt2	sat	sat	sat	0.01	0.01	0.01
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bit-vector_ab_br_max.smt2	sat	sat	sat	0.01	0.01	0.01
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_bit-vector_ab_cti_max.smt2	sat	sat	sat	0.01	0.01	0.01
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_blocks.2.prop1_ab_cti_max.smt2	sat	sat	sat	0.01	0.05	0.06
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_blocks.2.prop1_ab_reg_max.smt2	unsat	unsat	unsat	0.01	0.01	0.01
/home/simon/w/smtlib/QF_UF/2018-Goel-hwbench/QF_UF_blocks.3.prop1_ab_fp_max.smt2	sat	sat	sat	0.07	0.91	2.02

full results